A typical DC coupled Analog baseband chain 100 is depicted in FIG. 1. In those systems the signal is amplified by a Programmable Gain Amplifier (PGA) 101, filtered by the Low Pass Filter (LPF) 102 and then transferred to the Driver (DRV) 103. The active blocks are obtained with a closed loop DC coupled voltage amplifier or operational amplifier (OPAMP) 111, 112, 113. Key specifics of an OPAMP are noise, linearity and power consumption.
Since the useful signal contains also the DC component, the DC common mode has to be propagated along the chain and each of the blocks of the chain (PGA 101, LPF 102 and DRV 103) needs to comply with this DC common mode. This is also valid for the OPAMP 111, 112, 113 used in the analog blocks.
Key performances of an analog block like noise, linearity, power consumption, are also dictated by the performances of the OPAMP 111, 112, 113 used. Typically, for a given power consumption, there is a trade-off between noise and linearity. In FIGS. 2a and 2b an analog PGA 200 is shown (FIG. 2a) together with its OPAMP 201 (FIG. 2b). This PGA 200 is an implementation of the PGA 101 shown in FIG. 1. Note that the need to have an OPAMP with low output impedance dictates the use of a voltage follower as output stage.
The PGA 200 includes an operational amplifier 201 having a first (non-inverse, +) input VIN+, a second (inverse, −) input VIN−, a first (non-inverse, +) output VOUT+, a second (inverse, −) output VOUT−. A first feedback path including resistor R2 is coupled between output VOUT+ and input VIN+. A second feedback path including resistor R2 is coupled between output VOUT− and input VIN−. The first input VIN+ of OPAMP 201 is coupled via resistor R1 to a first input VC_IN+ of PGA 200. The second input VIN− of OPAMP 201 is coupled via resistor R1 to a second input VC_IN− of PGA 200. The first output VOUT+ of OPAMP 201 is the first output of PGA 200. The second output VOUT− of OPAMP 201 is the second output of PGA 200.
The OPAMP 201 includes a non-inverse input path between a drive voltage VDD and ground GND including a first (non-inverse) current source MP+, a first (non-inverse) transistor Q1+ and a second current source Io. A control terminal of Q1+ is coupled to the first input VIN+ of the OPAMP 201. The OPAMP 201 includes a non-inverse output path between a drive voltage VDD and ground GND including a second (non-inverse) transistor QF+ and a third current source Iout. A control terminal of QF+ is coupled to a first (non-inverse) internal node Vx+ of the OPAMP 201 which is located between MP+ and Q1+. A first terminal of QF+ is coupled to the first output VOUT+ of the OPAMP 201. A second terminal of QF+ is coupled to the drive voltage VDD. The above described components are additionally used in inverse form as described in the following.
The OPAMP 201 further includes an inverse input path between a drive voltage VDD and ground GND including a first (inverse) current source MP−, a first (inverse) transistor Q1− and a second current source Io. A control terminal of Q1− is coupled to the second input VIN− of the OPAMP 201. The OPAMP 201 includes an inverse output path between a drive voltage VDD and ground GND including a second (inverse) transistor QF− and a third current source Iout. A control terminal of QF− is coupled to a first (inverse) node Vx− of the OPAMP 201 which is located between MP− and Q1−. A first terminal of QF− is coupled to the second output VOUT− of the OPAMP 201. A second terminal of QF− is coupled to the drive voltage VDD.
A capacitance Cs and a resistor Rs are coupled in parallel between the first terminal of Q1+ and the first terminal of Q1−.
Note that the OPAMP 201 can be realized as a differential OPAMP as depicted in FIG. 2 or alternatively as a non-differential OPAMP. The non-differential OPAMP 201 has only one first current source MP, one first transistor Q1, one second current source Io, one third current source Iout, one input and one output without the differentiation of non-inverse and inverse components.
FIG. 3 is a circuit diagram of the OPAMP 201 shown in FIGS. 1 and 2a/b. The OPAMP 201 can be used in the Low Pass Filter 102 shown in FIG. 1 or more generally in a closed loop system like for example PGA or DRV, e.g. PGA 101 or DRV 103 as shown in FIG. 1. With reference to the OPAMP 201, the typical trade-off noise linearity can be understood by writing the equivalent input noise as:
      Vn    IN    2    =      4    ⁢          KT      ·              (                              1                                          g                                  m                  ⁢                                                                          ⁢                  1                                2                            ⁡                              (                                  Q                  1                                )                                              ⁢                      (                                                                                g                    m                                    ⁡                                      (                                          Q                      1                                        )                                                                    1                  +                                                                                    g                                                  m                          ⁢                                                                                                          ⁢                          1                                                                    ⁡                                              (                                                  Q                          1                                                )                                                              ·                    Rs                                                              +                              1                Rs                            +                                                2                  ·                  Io                                                  Vov                  ⁡                                      (                                          M                      P                                        )                                                                        )                          )            where the overdrive voltage Vov(MP)=Vgs(MP)−Vth(MP) is the difference between gate-source voltage of MP and its threshold voltage; gm(Q1) is the transconductance of transistor Q1; and Io is the bias current.
By inspecting the equation above it is clear that voltage referred input noise is reduced when Vov(MP) is maximized.
As far as linearity is concerned, OPAMP 201 will be linear until MP acts as a current mirror, i.e. MP stays in the saturation region. This condition is met with Vds(MP)>Vov(MP). Since Vds(MP) will be set by maximum signal level, this means that linearity is maximized if Vov(MP) is minimized.
The trade-off on the choice of overdrive voltage Vov(MP) means that noise and linearity are conflicting requirements.
The addition of the DC common mode requirement makes things more complicated. In fact, to avoid a DC current going in or out of the LPF, the common mode of the input and output signals have to be the same. Furthermore, input and output common modes of the LPF are also dictated by preceding and following stages: this plus the need to have same common mode for input and output signals poses a considerable challenge, since input and output DC voltages that maximize linearity are not necessarily the same.
The additional constraint on linearity performance due to the DC coupled implementation is depicted in FIGS. 4a and 4b. In the assumption that the preceding stage set the common mode to VDD/2=1.25V, the voltage Vx at the base of the voltage follower will be ˜2.05V. This voltage will make transistors MP compress much earlier than transistors Q1; therefore it is not optimal for linearity.
In this specific case, a lower common mode voltage at the input would improve headroom for MP transistor and overall linearity (current generators at the emitter of Q1 and Q2 have still enough headroom with the equivalent input signal level of FIG. 4) as illustrated in FIGS. 5a and 5b. Furthermore, but as anticipated before, when the filter is used in a communication system, DC points can be a function of preceding/following stages, therefore it is not always possible to set them to the level that maximises linearity.